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[VHDL-FPGA-Verilog] T4_sdram_control

Description: verilog语言 利用FPGA控制SDRAM，相信很多朋友都需要 快下载吧-control FPGA Verilog language use SDRAM, believe that many of my friends need to download it faster
Platform: | Size: 19456 | Author: 杜菲 | Hits:

[VHDL-FPGA-Verilog] VerilogSDRAMcontry

Description: 本文档是一个使用VERILOG语言所讨论的上SDRAM的基本原理！
Platform: | Size: 4096 | Author: JP | Hits:

[VHDL-FPGA-Verilog] sdram_0

Description: SDRAM的Verilog HDL程序，适合DE2开发板，和TRDB-LCM显示器，很好哦-SDRAM procedures of the Verilog HDL for DE2 development board, and TRDB-LCM display, oh well
Platform: | Size: 4096 | Author: 白雪 | Hits:

[VHDL-FPGA-Verilog] SDR_SDRAM_controler_verilog

Description: 可以用的通用SDRAM控制器,可以用在FPGA上,是SDR类型的-Can use the generic SDRAM controller can be used in the FPGA, the SDR is the type of
Platform: | Size: 9216 | Author: 郑宏超 | Hits:

[Other Embeded program] Sdram_Control_4Port

Description: sopc sdram 硬核的verilog 源码-sopc sdram hard core of the Verilog source code
Platform: | Size: 13312 | Author: wxx | Hits:

[Other] sdram_all

Description: sdram 控制器的verilog 实现，包括用户逻辑和控制器的设计-SDRAM controller Verilog realization, including user logic and controller design
Platform: | Size: 505856 | Author: shroy | Hits:

[VHDL-FPGA-Verilog] newSD

Description: 基于Verilog的完整SDRAM控制器时序代码-Based on a complete Verilog timing SDRAM controller code
Platform: | Size: 4096 | Author: 云 | Hits:

[VHDL-FPGA-Verilog] SDRAM_simulation_model

Description: sdram的测试程序 和读写程序 vhdl语言编写的-SDRAM testing procedures and to read and write procedures VHDL language
Platform: | Size: 93184 | Author: 朱宝军 | Hits:

[VHDL-FPGA-Verilog] VerilogfoFPGAbasedSDRAMController

Description: 使用Verilog实现基于FPGA的SDRAM控制器-The use of Verilog for FPGA-based SDRAM Controller
Platform: | Size: 1680384 | Author: he | Hits:

[Embeded-SCM Develop] hssdrc_latest

Description: SDRAM 控制器 Verilog实现，很有借鉴意义。-SDRAM controller core Verilog implementation。With good referential significance.
Platform: | Size: 424960 | Author: metallica | Hits:

[VHDL-FPGA-Verilog] SDRAM_VerilogCode

Description: 基于FPGA的SDRAM控制器Verilog代码，开发环境为Quartus6.1，控制SDRAM实现对同一片地址先写后读。-FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to write.
Platform: | Size: 26624 | Author: 姜琰俊 | Hits:

[VHDL-FPGA-Verilog] webCam-FPGA

Description: 使用Verilog控制美光CMOS图像处理器，并转存到SDRAM中。使用FPGA为QL的带fuse系列-Control the use of Verilog Micron CMOS image processor and SDRAM in转存到. FPGA for use with QL series fuse
Platform: | Size: 36864 | Author: NOOW | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[VHDL-FPGA-Verilog] sdram_verilog

Description: sdram的使用，使用verilog HDL来实现对sdram的操作！对时序和语言功底有要求！-sdram use verilog HDL used to achieve operation of the sdram! On the timing and language skills required!
Platform: | Size: 69632 | Author: wang | Hits:

[VHDL-FPGA-Verilog] SDRAM_controler_code

Description: SDRAM的verilog控制器代码极其仿真模块-The verilog code for SDRAM controller is extremely Simulation Module
Platform: | Size: 194560 | Author: 周仁杰 | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
Platform: | Size: 678912 | Author: liujie | Hits:

[VHDL-FPGA-Verilog] HY57V641620HG.vp

Description: Hynix公司8M Byte SDR SDRAM的Verilog语言仿真实现-Hynix' s 8M Byte SDR SDRAM Simulation of the Verilog language
Platform: | Size: 54272 | Author: tom | Hits:

[VHDL-FPGA-Verilog] mt48lc4m32b2.v

Description: SDRAM VHDL/Verilog simulation model
Platform: | Size: 7168 | Author: Ravi | Hits:

[VHDL-FPGA-Verilog] sdram_vhd_134

Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
Platform: | Size: 488448 | Author: peace | Hits:

[Other] yuqix_datum

Description: i2cinterface.v是我自己写的一段verilog代码，在接口为I2C接口的芯片设计中用到。送去流过片，仅作参考用。 debussy和modelsim协同仿真.txt 用于debussy和modelsim协同仿真时参考 RTL Coding and Optimization Guide for use with Design Compiler.pdf 数提讲座（1）.wmv 数提讲座（2）.wmv这两个视频和一篇文档对数字IC前端设计师的设计提高很有帮助，如果你觉得你到瓶颈状态了，想提高的话，强烈建议好好看看。 ADVANCED ASIC CHIP SYNTHESIS中文翻译资料.ppt这也是我极力推荐的，相信学习dc的人都知道原英文文档。这个ppt相当于翻译版，对dc和pt中文详细阐述。 基于DDR SDRAM控制时序分析的模型.pdf 全定制单元时序模型的建立.pdf 这两篇文档是用作建议时序模型的时候用作参考，是我花了小money买的哦。 数字IC设计全程实例.pdf 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从设计的系统行为级描述或RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真. -i2cinterface.v a section of my own writing verilog code for the I2C interface in the interface used in chip design. Sent to flow through the film, only for reference. debussy and modelsim co-simulation. txt for debussy and modelsim co-simulation reference RTL Coding and Optimization Guide for use with Design Compiler.pdf Mention the number of lectures (1). Wmv Mention the number of lectures (2). Wmv the two videos, and the document is useful for the digital front-end IC designers to improve the design capability. if you think you go to bottleneck, and want to improve, then it is strongly recommended a good look. ADVANCED ASIC CHIP SYNTHESIS Chinese translation of the information. Ppt that is what I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese . DDR SDRAM control the timing analysis based on the model. Pdf
Platform: | Size: 20989952 | Author: 喻琪 | Hits:
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